Video display systems based on spatial light modulators (SLMs) are increasingly being used as an alternative to display systems using cathode ray tubes (CRTs). SLM systems provide high resolution displays without the bulk and power consumption of CRT systems.
Digital micro-mirror devices (DMDs) are a type of SLM, and may be used for either direct-view or projection display applications. A DMD has an array of micro-mechanical pixels, each having a tiny mirror that is individually addressable by an electronic signal Depending on the state of its addressing signal, each mirror tilts so that it either does or does not reflect light to the image plane. The mirrors are often referred to as "pixels," to correspond to the pixels of the image that they generate. Generally, displaying pixel data is accomplished by loading memory cells connected to the pixels. The pixels can maintain their on or off state for controlled display times.
Other SLMs operate on similar principles, with an array of pixels that may emit or reflect light simultaneously, such that a complete image is generated by addressing pixels rather than by scanning a screen. Another example of an SLM is a liquid crystal display (LCD) having individually driven pixels.
To achieve intermediate levels of illumination, between white (on) and black (off), pulse-width modulation (PWM) techniques are used. The basic PWM scheme involves first determining the rate at which images are to be presented to the viewer. This establishes a frame rate and a corresponding frame period. For example, in a standard television system, images are transmitted at 30 frames per second, and each frame lasts for approximately 33.3 milliseconds. Then, the intensity resolution for each pixel is established. In a simple example, and assuming n bits of resolution, the frame time is divided into 2.sup.n -1 equal time slices. For a 33.3 millisecond frame period and n-bit intensity values, the time slice is 33.3/(2.sup.n -1) milliseconds.
Having established these times, for each pixel of each frame, pixel intensities are quantized, such that black is 0 time slices, the intensity level represented by the LSB is 1 time slice, and maximum brightness is 2.sup.n 1-time slices. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is on for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMs, PWM calls for the data to be formatted into "bit-planes," each bit-plane corresponding to a bit weight of the intensity value. Thus, if each pixel's intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each pixel. In the simple PWM example described in the preceding paragraphs, during a frame, each bit-plane is separately loaded and the pixels addressed according to their associated bit-plane values. For example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs is displayed for 2n/2 time slices. Because a time slice is only 33.3/(2.sup.n -1) milliseconds, the SLM must be capable of loading the LSB bit-plane within that time. The time for loading the LSB bit-plane is the "peak data rate."
U.S. Pat. No. 5278,652, entitled "DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System," assigned to Texas Instruments Incorporated describes various methods of addressing a DMD in a DMD-based display system. These methods are directed to reducing the peak data rate while maintaining optical efficiency. Some of the methods discussed therein include clearing blocks of pixel elements and using extra "off" times to load data. In one method the time in which the most significant bit is displayed is broken into smaller segments so as to permit loading for less significant bits to occur during these segments.
Another method of reducing the peak data rate is referred to as "memory multiplexing" or "split reset." This method uses a specially configured SLM, whose pixels are grouped into reset groups that are separately loaded and addressed. This reduces the amount of data to be loaded during any one times and permits the LSB data for each reset group to be loaded at a different time during the frame period. This configuration is described in U.S. patent Ser. No. 08/002,627 assigned to Texas Instruments Incorporated.
Regardless of whether or not the pixels of the SLM are addressed all at once or are multiplexed, the resulting display must have minimal visual artifacts. A type of artifact that is possible with bit-plane data is "temporal contouring." As an example, for an 8-bit system, if in one frame, a pixel has an intensity level of 128 and the MSB display time occurs during the first half of the frame time, the pixel is on for this length of time and off for the rest of the frame time. If, in the next frame, the pixel's intensity is 127, the pixel is off for the MSB time and on during the display time for all other bits during that frame. The point in time when all bits change state can cause a visual artifact, which is more perceptible as brightness increases.